Tuesday, January 15, 2013What is “Register-less Architecture”?“Register-less Architecture” is literally an architecture of a microprocessor omitting register. That said, a processor with no register cannot do anything. Therefore, the processor in this case has minimal register and can also use its main memory as general-purpose register. Several classic processors prior to RISC substituted part of main memory for register. Current high-performance processors, operating by GHz unit internally, depend on lots of register and cache memory. However, the circumstances are different when we use a FPGA as a microcontroller accommodating main memory and a processor. This configuration has no need of external memory, but has to allocate the precious internal memory resource to register file and main memory. Therefore, the more register turns to be the less main memory. As the register and the main memory use the same internal memory after all, there is little effect in reducing access to main memory by using register. In this context, the primary feature of the “register-less architecture” is that the entire memory embedded in a FPGA is available as main memory. Another significant feature of the architecture is multi-core availability. Designing mainboard may sound like mission impossible to hobby users, once multiprocessors emit high-speed signals externally on PCB, but it is achievable just by struggling with EDA tools, as long as it is all about inside FPGA. Once packing multi-core processor and main memory into a FPGA, all you need is a hardware description language for complete design. Therefore, this would be almost the only way for hobby users to design a system with multi-core so far. However, this method requires a multi-core processor with (commonly incredible) compact circuit so as to fit in a FPGA unit. Register-less architecture also serves as a design methodology for it. To be continued… |
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